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INTEGRATED CIRCUITS
74F50728 Synchronizing cascaded dual positive edge-triggered D-type flip-flop
Positive specification IC15 Data Handbook 1990 Sep 14
Philips Semiconductors
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
FEATURES
* Metastable immune characteristics * Output skew less than 1.5ns * See 74F5074 for synchronizing dual D-type flip-flop * See 74F50109 for synchronizing dual J-K positive edge-triggered
flip-flop
Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the Dn input may be changed without affecting the levels of the output. Data entering the 74F50728 requires two clock cycles to arrive at the outputs. The 74F50728 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50728 are: 135ps and T0 9.8 X 106 sec where represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a function of the measurement of the propensity of a latch to enter a metastable state. TYPICAL SUPPLY CURRENT (TOTAL) 23mA
* See 74F50729
for synchronizing dual dual D-type flip-flop with edge-triggered set and reset
* Industrial temperature range available (-40C to +85C)
DESCRIPTION
The 74F50728 is a cascaded dual positive edge-triggered D-type featuring individual data, clock, set and reset inputs; also true and complementary outputs. Set (SDn) and reset (RDn) are asynchronous active low inputs and operate independently of the clock (CPn) input. They set and reset both flip-flops of a cascaded pair simultaneously. Data must be stable just one setup time prior to the low-to-high transition of the clock for guaranteed propagation delays.
TYPE 74F50728
TYPICAL fmax 145 MHz
ORDERING INFORMATION
ORDER CODE COMMERCIAL RANGE DESCRIPTION VCC = 5V 10%, Tamb = 0C to +70C 14-pin plastic DIP 14-pin plastic SO N74F50728N N74F50728D INDUSTRIAL RANGE VCC = 5V 10%, Tamb = -40C to +85C I74F50728N I74F50728D SOT27-1 SOT108-1 PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS D0, D1 CP0, CP1 SD0, SD1 RD0, RD1 Data inputs Clock inputs (active rising edge) Set inputs (active low) Reset inputs (active low) DESCRIPTION 74F (U.L.) HIGH/ LOW 1.0/0.417 1.0/1.0 1.0/1.0 1.0/1.0 50/33 LOAD VALUE HIGH/ LOW 20A/250A 20A/20A 20A/20A 20A/20A 1.0mA/20mA
Q0, Q1, Q0, Q1 Data outputs NOTE: One (1.0) FAST unit load is defined as: 20A in the high state and 0.6mA in the low state.
September 14, 1990
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853-1389 00421
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
PIN CONFIGURATION
LOGIC DIAGRAM
4, 10 SDn
RD0 1 D0 2 CP0 3 SD0 4 Q0 5 Q0 6 GND 7
14 VCC 13 RD1 12 D1 11 CP1 10 SD1 9 Q1 8 Q1 Vcc = Pin 14 GND = Pin 7 CPn RDn 3, 11 1, 13 2, 12 Dn D Q D Q 5, 9 Qn 6, 8 Qn
CP Q
CP Q
SF00608
SF00605
NOTE: Data entering the flip-flop requires two clock cycles to arrive at the output.
LOGIC SYMBOL SYNCHRONIZING SOLUTIONS
2 12 D0 D1 3 4 1 11 10 13 CP0 SD0 RD0 CP1 SD1 RD1 Q0 Q0 Q1 Q1
5 VCC = Pin 14 GND = Pin 7
6
9
8
SF00606
IEC/IEEE SYMBOL
4 3 2 1 1D 6 R & S C1 3
Synchronizing incoming signals to a system clock has proven to be costly, either in terms of time delays or hardware. The reason for this is that in order to synchronize the signals a flip-flop must be used to "capture" the incoming signal. While this is perhaps the only way to synchronize a signal, to this point, there have been problems with this method. Whenever the flop's setup or hold times are violated the flop can enter a metastable state causing the outputs in turn to glitch, oscillate, enter an intermediate state or change state in some abnormal fashion. Any of these conditions could be responsible for causing a system crash. To minimize this risk, flip-flops are often cascaded so that the input signal is captured on the first clock pulse and released on the second clock pulse (see Fig.1). This gives the first flop about one clock period minus the flop delay and minus the second flop's clock-to-Q setup time to resolve any metastable condition. This method greatly reduces the probability of the outputs of the synchronizing device displaying an abnormal state but the trade-off is that one clock cycle is lost to synchronize the incoming data and two separate flip-flops are required to produce the cascaded flop circuit. In order to assist the designer of synchronizing circuits Philips Semiconductors is offering the 74F50728.
DATA CLOCK
D
Q
D
Q
Q OUTPUT Q OUTPUT
CP Q
CP Q
10 11 12 13
S C2
9
SF00609
Figure 1.
2D 8 R
SF00607
The 50728 consists of two pair of cascaded D-type flip-flops with metastable immune features and is pin compatible with the 74F74. Because the flops are cascaded on a single part the metastability
September 14, 1990
3
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
characteristics are greatly improved over using two separate flops that are cascaded. The pin compatibility with the 74F74 allows for plug-in retrofitting of previously designed systems. Because the probability of failure of the 74F50728 is so remote, the metastability characteristics of the part were empirically determined based on the characteristics of its sister part, the 74F5074. The table below shows the 74F5074 metastability characteristics. Having determined the T0 and of the flop, calculating the mean time between failures (MTBF) for the 74F50728 is simple. It is, however, somewhat different than calculating MTBF for a typical part because data requires two clock pulses to transit from the input to the output. Also, in this case a failure is considered of the output beyond the normal propagation delay.
Suppose a designer wants to use the flop for synchronizing asynchronous data that is arriving at 10MHz (as measured by a frequency counter), and is using a clock frequency of 50MHz. He simply plugs his number into the equation below: MTBF = e(t'/t)/TofCfI In this formula, fC is the frequency of the clock, fI is the average input event frequency, and t' is the period of the clock input (20 nanoseconds). In this situation the fI will be twice the data frequency of 20 MHz because input events consist of both of low and high data transitions. From Fig. 2 it is clear that the MTBF is greater than 1041 seconds. Using the above formula the actual MTBF is 2.23 X 1042 seconds or about 7 X 1034 years.
TYPICAL VALUES FOR AND T0 AT VARIOUS VCCS AND TEMPERATURES
Tamb = 0C VCC = 5.5V VCC = 5.0V VCC = 4.5V 125ps 115ps 115ps 1.0 X T0 109 sec 138ps 135ps 132ps 5.4 X Tamb = 25C T0 106 sec 160ps 167ps 175ps Tamb = 70C T0 1.7 X 105 sec 3.9 X 104 sec 7.3 X 104 sec
1.3 X 1010 sec 3.4 X 1013 sec
9.8 X 106 sec 5.1 X 108 sec
MEAN TIME BETWEEN FAILURES VERSUS DATA FREQUENCY AT VARIOUS CLOCK FREQUENCY
1070 Clock = 40MHz 1060
1050 Mean time between failures (seconds) 1040 Clock = 650MHz 1030 Clock = 70MHz Clock = 80MHz 1020 1 billion years 1010 Clock = 100MHz Clock = 50MHz
1000 1K NOTE: VCC = 5V, Tamb = 25C, =135ps, To = 9.8 X 108 sec Data frequency (Hz) 100K 10M
SF00610
Figure 2.
September 14, 1990
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Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
FUNCTION TABLE
INTERNAL INPUTS SDn L H L H H H RDn H L L H H H CPn X X X L Dn X X X h l X REGISTER Q H L X h l NC OUTPUTS Qn H L H H L NC Qn L H H L H NC Asynchronous set Asynchronous reset Undetermined* Load "1" Load "0" Hold OPERATING MODE
NOTES: H = High voltage level h = High voltage level one setup time prior to low-to-high clock transition L = Low voltage level l = Low voltage level one setup time prior to low-to-high clock transition
NC= No change from the previous setup X = Don't care * = This setup is unstable and will change when either set of reset return to the high-level = Low-to-high clock transition. ** = Data entering the flip-flop requires two clock cycles to arrive at the output (see logic diagram)
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL VCC VIN IIN VOUT IOUT Tamb Supply voltage Input voltage Input current Voltage applied to output in high output state Current applied to output in low output state Operating free air temperature range Commercial range Industrial range Tstg Storage temperature range PARAMETER RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to VCC 40 0 to +70 -40 to +85 -65 to +150 UNIT V V mA V mA
C C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER MIN VCC VIH VIL IIk IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current Low-level output current Operating free air temperature range Commercial range Industrial range 0 -40 4.5 2.4 0.8 -18 -3 20 +70 +85 LIMITS NOM 5.0 MAX 5.5 UNIT V V V mA mA mA
C C
September 14, 1990
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Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL PARAMETER TEST CONDITIONS1 VOH High-level output voltage VCC = MIN, VIH = MIN VIL = MAX, VOL Low-level output voltage VCC = MIN, VIL = MAX, VIH = MIN VIK II IIH IIL IOS Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current Short-circuit output current3 Dn CPn, SDn, RDn VCC = MAX, VO = 2.25V -60 VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V IOL = MAX IOH = MAX MIN LIMITS TYP2 MAX V 3.4 0.30 0.30 -0.73 0.50 0.50 -1.2 100 20 -250 -20 -150 V V V V A A A A mA UNIT
10%VCC 5%VCC 10%VCC 5%VCC
2.5 2.7
ICC Supply current4 (total) VCC = MAX 23 34 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN fmax tPLH tPHL tPLH tPHL Maximum clock frequency Propagation delay CPn to Qn or Qn Propagation delay SDn RDn to Qn or Qn Waveform 1 Waveform 1 Waveform 2 100 2.0 2.0 3.5 3.5 TYP 145 3.8 3.8 5.0 5.0 6.0 6.0 8.0 8.0 MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 85 1.5 2.0 3.0 3.0 6.5 6.5 9.0 8.5 MAX Tamb = -40C to +85C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 70 1.5 2.0 3.0 3.0 7.5 7.0 10.5 10.0 1.5 MAX ns ns ns ns UNIT
tsk(o) Output skew1, 2 Waveform 4 1.5 1.5 NOTES TO AC ELECTRICAL CHARACTERISTICS 1. | tPLH actual -tPHL actual | for any one output compare to any other output where N and M are either LH or HL. 2. Skew lines are valid only under same conditions (temperature, VCC, loading, etc.,).
September 14, 1990
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Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
AC SETUP REQUIREMENTS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITION VCC = +5.0V CL = 50pF, RL = 500 MIN tsu (H) tsu(L) th (H) th (L) tw (H) tw (L) tw (L) trec Setup time, high or low Dn to CPn Hold time, high or low Dn to CPn CPn pulse width, high or low SDn, RDn pulse width, low Recovery time SDn, RDn to CPn Waveform 1 Waveform 1 Waveform 2 Waveform 2 Waveform 3 1.5 1.5 0.0 0.0 3.0 4.0 4.5 3.5 TYP MAX Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.0 2.0 1.5 1.5 3.5 5.0 4.0 3.5 MAX Tamb = -40C to +85C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 2.0 2.0 1.5 1.5 4.0 5.5 4.5 3.5 MAX ns ns ns ns ns UNIT
AC WAVEFORMS
Jn, Kn VM tsu(L) VM th(L) 1/fmax CPn RDn VM tw(H) tPLH Qn VM tPHL Qn VM tw(L) VM VM tPLH tPHL Qn VM tPHL tPLH Qn VM VM VM tPLH VM VM VM tPHL VM tsu(H) VM th(H) tw(L) VM tw(L) VM
SDn VM
SF00050 SF00139
Waveform 1. Propagation delay for data to output, data setup time and hold times, and clock width, and maximum clock frequency
Waveform 2. Propagation delay for set and reset to output, set and reset pulse width
Qn, Qn
VM tsk(o)
SDn or RDn
VM trec Qn, Qn
VM
CPn
VM
SF00590 SF00603
Waveform 4. Output skew
Waveform 3. Recovery time for set or reset to output NOTES: For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance.
September 14, 1990
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Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
TEST CIRCUIT AND WAVEFORMS
VCC NEGATIVE PULSE VIN PULSE GENERATOR RT D.U.T. VOUT 90% VM 10% tTHL (tf ) CL RL tw VM 10% tTLH (tr ) 0V 90% AMP (V)
tTLH (tr ) 90% POSITIVE PULSE VM 10% tw
tTHL (tf ) AMP (V) 90% VM 10% 0V
Test Circuit for Totem-Pole Outputs DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00006
September 14, 1990
8
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
1990 Sep 14
9
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
1990 Sep 14
10
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
NOTES
1990 Sep 14
11
Philips Semiconductors
Product specification
Synchronizing cascaded dual positive edge-triggered D-type flip-flop
74F50728
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 10-98 9397-750-05215
Philips Semiconductors
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